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<div class="title">xnandpsu_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga04482e1a4b37499e238e82b3052ea587"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga04482e1a4b37499e238e82b3052ea587">XNANDPSU_PKT_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga04482e1a4b37499e238e82b3052ea587"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Register.  <a href="group__nandpsu__v1__0.html#ga04482e1a4b37499e238e82b3052ea587">More...</a><br /></td></tr>
<tr class="separator:ga04482e1a4b37499e238e82b3052ea587"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8332ffd41c06df1898fb85c3d0a2264c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga8332ffd41c06df1898fb85c3d0a2264c">XNANDPSU_MEM_ADDR1_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga8332ffd41c06df1898fb85c3d0a2264c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory Address Register 1.  <a href="group__nandpsu__v1__0.html#ga8332ffd41c06df1898fb85c3d0a2264c">More...</a><br /></td></tr>
<tr class="separator:ga8332ffd41c06df1898fb85c3d0a2264c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed3f1b12deeb3408475e87ed937e1440"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaed3f1b12deeb3408475e87ed937e1440">XNANDPSU_MEM_ADDR2_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:gaed3f1b12deeb3408475e87ed937e1440"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory Address Register 2.  <a href="group__nandpsu__v1__0.html#gaed3f1b12deeb3408475e87ed937e1440">More...</a><br /></td></tr>
<tr class="separator:gaed3f1b12deeb3408475e87ed937e1440"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a770f895919f2a9f22b109fc2dc4ddd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga8a770f895919f2a9f22b109fc2dc4ddd">XNANDPSU_CMD_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:ga8a770f895919f2a9f22b109fc2dc4ddd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Register.  <a href="group__nandpsu__v1__0.html#ga8a770f895919f2a9f22b109fc2dc4ddd">More...</a><br /></td></tr>
<tr class="separator:ga8a770f895919f2a9f22b109fc2dc4ddd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd02fc694047f74abeeec4f52bfd384d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gadd02fc694047f74abeeec4f52bfd384d">XNANDPSU_PROG_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:gadd02fc694047f74abeeec4f52bfd384d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Program Register.  <a href="group__nandpsu__v1__0.html#gadd02fc694047f74abeeec4f52bfd384d">More...</a><br /></td></tr>
<tr class="separator:gadd02fc694047f74abeeec4f52bfd384d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3b3c15277fa67d8d1dd55492fa3173a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf3b3c15277fa67d8d1dd55492fa3173a">XNANDPSU_INTR_STS_EN_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:gaf3b3c15277fa67d8d1dd55492fa3173a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Enable Register.  <a href="group__nandpsu__v1__0.html#gaf3b3c15277fa67d8d1dd55492fa3173a">More...</a><br /></td></tr>
<tr class="separator:gaf3b3c15277fa67d8d1dd55492fa3173a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a25f700e1e33ac4bdb4be3681fdb477"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga8a25f700e1e33ac4bdb4be3681fdb477">XNANDPSU_INTR_SIG_EN_OFFSET</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:ga8a25f700e1e33ac4bdb4be3681fdb477"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Signal Enable Register.  <a href="group__nandpsu__v1__0.html#ga8a25f700e1e33ac4bdb4be3681fdb477">More...</a><br /></td></tr>
<tr class="separator:ga8a25f700e1e33ac4bdb4be3681fdb477"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6809a4525da95b43bdfcf841e679698a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6809a4525da95b43bdfcf841e679698a">XNANDPSU_INTR_STS_OFFSET</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:ga6809a4525da95b43bdfcf841e679698a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__nandpsu__v1__0.html#ga6809a4525da95b43bdfcf841e679698a">More...</a><br /></td></tr>
<tr class="separator:ga6809a4525da95b43bdfcf841e679698a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd2d6d5ea689b58c981538948fe32e10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gabd2d6d5ea689b58c981538948fe32e10">XNANDPSU_READY_BUSY_OFFSET</a>&#160;&#160;&#160;0x20U</td></tr>
<tr class="memdesc:gabd2d6d5ea689b58c981538948fe32e10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ready/Busy status Register.  <a href="group__nandpsu__v1__0.html#gabd2d6d5ea689b58c981538948fe32e10">More...</a><br /></td></tr>
<tr class="separator:gabd2d6d5ea689b58c981538948fe32e10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5f11ea56bdac764873705a28405205f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gab5f11ea56bdac764873705a28405205f">XNANDPSU_FLASH_STS_OFFSET</a>&#160;&#160;&#160;0x28U</td></tr>
<tr class="memdesc:gab5f11ea56bdac764873705a28405205f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash Status Register.  <a href="group__nandpsu__v1__0.html#gab5f11ea56bdac764873705a28405205f">More...</a><br /></td></tr>
<tr class="separator:gab5f11ea56bdac764873705a28405205f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5323a1a40087286e737def2534d90e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf5323a1a40087286e737def2534d90e6">XNANDPSU_TIMING_OFFSET</a>&#160;&#160;&#160;0x2CU</td></tr>
<tr class="memdesc:gaf5323a1a40087286e737def2534d90e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Register.  <a href="group__nandpsu__v1__0.html#gaf5323a1a40087286e737def2534d90e6">More...</a><br /></td></tr>
<tr class="separator:gaf5323a1a40087286e737def2534d90e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1890472a2b558a5800d21e32c78b6d30"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1890472a2b558a5800d21e32c78b6d30">XNANDPSU_BUF_DATA_PORT_OFFSET</a>&#160;&#160;&#160;0x30U</td></tr>
<tr class="memdesc:ga1890472a2b558a5800d21e32c78b6d30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Data Port Register.  <a href="group__nandpsu__v1__0.html#ga1890472a2b558a5800d21e32c78b6d30">More...</a><br /></td></tr>
<tr class="separator:ga1890472a2b558a5800d21e32c78b6d30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc4b3c32366da83a20eef8095b80bd25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gacc4b3c32366da83a20eef8095b80bd25">XNANDPSU_ECC_OFFSET</a>&#160;&#160;&#160;0x34U</td></tr>
<tr class="memdesc:gacc4b3c32366da83a20eef8095b80bd25"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC Register.  <a href="group__nandpsu__v1__0.html#gacc4b3c32366da83a20eef8095b80bd25">More...</a><br /></td></tr>
<tr class="separator:gacc4b3c32366da83a20eef8095b80bd25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14a27b4f50dae98e829483817b036e9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga14a27b4f50dae98e829483817b036e9e">XNANDPSU_ECC_ERR_CNT_OFFSET</a>&#160;&#160;&#160;0x38U</td></tr>
<tr class="memdesc:ga14a27b4f50dae98e829483817b036e9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC Error Count Register.  <a href="group__nandpsu__v1__0.html#ga14a27b4f50dae98e829483817b036e9e">More...</a><br /></td></tr>
<tr class="separator:ga14a27b4f50dae98e829483817b036e9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6bbee4cc41eb49c38026cef011117911"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6bbee4cc41eb49c38026cef011117911">XNANDPSU_ECC_SPR_CMD_OFFSET</a>&#160;&#160;&#160;0x3CU</td></tr>
<tr class="memdesc:ga6bbee4cc41eb49c38026cef011117911"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC Spare Command Register.  <a href="group__nandpsu__v1__0.html#ga6bbee4cc41eb49c38026cef011117911">More...</a><br /></td></tr>
<tr class="separator:ga6bbee4cc41eb49c38026cef011117911"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa6af724c38008c62af9e04e835f674de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa6af724c38008c62af9e04e835f674de">XNANDPSU_ECC_CNT_1BIT_OFFSET</a>&#160;&#160;&#160;0x40U</td></tr>
<tr class="memdesc:gaa6af724c38008c62af9e04e835f674de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 1bit Register.  <a href="group__nandpsu__v1__0.html#gaa6af724c38008c62af9e04e835f674de">More...</a><br /></td></tr>
<tr class="separator:gaa6af724c38008c62af9e04e835f674de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga113ad40b30839f92d3fb32c4eb32cda6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga113ad40b30839f92d3fb32c4eb32cda6">XNANDPSU_ECC_CNT_2BIT_OFFSET</a>&#160;&#160;&#160;0x44U</td></tr>
<tr class="memdesc:ga113ad40b30839f92d3fb32c4eb32cda6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 2bit Register.  <a href="group__nandpsu__v1__0.html#ga113ad40b30839f92d3fb32c4eb32cda6">More...</a><br /></td></tr>
<tr class="separator:ga113ad40b30839f92d3fb32c4eb32cda6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a76ee78e6ef81ce10f36332fa35c335"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga0a76ee78e6ef81ce10f36332fa35c335">XNANDPSU_ECC_CNT_3BIT_OFFSET</a>&#160;&#160;&#160;0x48U</td></tr>
<tr class="memdesc:ga0a76ee78e6ef81ce10f36332fa35c335"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 3bit Register.  <a href="group__nandpsu__v1__0.html#ga0a76ee78e6ef81ce10f36332fa35c335">More...</a><br /></td></tr>
<tr class="separator:ga0a76ee78e6ef81ce10f36332fa35c335"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa29bfde2fa3767d6c75cdc481eb1f828"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa29bfde2fa3767d6c75cdc481eb1f828">XNANDPSU_ECC_CNT_4BIT_OFFSET</a>&#160;&#160;&#160;0x4CU</td></tr>
<tr class="memdesc:gaa29bfde2fa3767d6c75cdc481eb1f828"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 4bit Register.  <a href="group__nandpsu__v1__0.html#gaa29bfde2fa3767d6c75cdc481eb1f828">More...</a><br /></td></tr>
<tr class="separator:gaa29bfde2fa3767d6c75cdc481eb1f828"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf10e945915722b188807af980c2efe96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf10e945915722b188807af980c2efe96">XNANDPSU_CPU_REL_OFFSET</a>&#160;&#160;&#160;0x58U</td></tr>
<tr class="memdesc:gaf10e945915722b188807af980c2efe96"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU Release Register.  <a href="group__nandpsu__v1__0.html#gaf10e945915722b188807af980c2efe96">More...</a><br /></td></tr>
<tr class="separator:gaf10e945915722b188807af980c2efe96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9804e05977896127c90dbefc67395634"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga9804e05977896127c90dbefc67395634">XNANDPSU_ECC_CNT_5BIT_OFFSET</a>&#160;&#160;&#160;0x5CU</td></tr>
<tr class="memdesc:ga9804e05977896127c90dbefc67395634"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 5bit Register.  <a href="group__nandpsu__v1__0.html#ga9804e05977896127c90dbefc67395634">More...</a><br /></td></tr>
<tr class="separator:ga9804e05977896127c90dbefc67395634"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga527de0539b282e03ee0c1645c88dbe47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga527de0539b282e03ee0c1645c88dbe47">XNANDPSU_ECC_CNT_6BIT_OFFSET</a>&#160;&#160;&#160;0x60U</td></tr>
<tr class="memdesc:ga527de0539b282e03ee0c1645c88dbe47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 6bit Register.  <a href="group__nandpsu__v1__0.html#ga527de0539b282e03ee0c1645c88dbe47">More...</a><br /></td></tr>
<tr class="separator:ga527de0539b282e03ee0c1645c88dbe47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga610b05baec03fc0018cedf3c308d653c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga610b05baec03fc0018cedf3c308d653c">XNANDPSU_ECC_CNT_7BIT_OFFSET</a>&#160;&#160;&#160;0x64U</td></tr>
<tr class="memdesc:ga610b05baec03fc0018cedf3c308d653c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 7bit Register.  <a href="group__nandpsu__v1__0.html#ga610b05baec03fc0018cedf3c308d653c">More...</a><br /></td></tr>
<tr class="separator:ga610b05baec03fc0018cedf3c308d653c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60fd7f278f66bd43e44c51fa0b9ca75e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga60fd7f278f66bd43e44c51fa0b9ca75e">XNANDPSU_ECC_CNT_8BIT_OFFSET</a>&#160;&#160;&#160;0x68U</td></tr>
<tr class="memdesc:ga60fd7f278f66bd43e44c51fa0b9ca75e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Count 8bit Register.  <a href="group__nandpsu__v1__0.html#ga60fd7f278f66bd43e44c51fa0b9ca75e">More...</a><br /></td></tr>
<tr class="separator:ga60fd7f278f66bd43e44c51fa0b9ca75e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5efd1c0220097175784dd8da2cddd526"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga5efd1c0220097175784dd8da2cddd526">XNANDPSU_DATA_INTF_OFFSET</a>&#160;&#160;&#160;0x6CU</td></tr>
<tr class="memdesc:ga5efd1c0220097175784dd8da2cddd526"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface Register.  <a href="group__nandpsu__v1__0.html#ga5efd1c0220097175784dd8da2cddd526">More...</a><br /></td></tr>
<tr class="separator:ga5efd1c0220097175784dd8da2cddd526"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4243b86bd0cbfdc5297e2cf36a2fa090"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga4243b86bd0cbfdc5297e2cf36a2fa090">XNANDPSU_DMA_SYS_ADDR0_OFFSET</a>&#160;&#160;&#160;0x50U</td></tr>
<tr class="memdesc:ga4243b86bd0cbfdc5297e2cf36a2fa090"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA System Address 0 Register.  <a href="group__nandpsu__v1__0.html#ga4243b86bd0cbfdc5297e2cf36a2fa090">More...</a><br /></td></tr>
<tr class="separator:ga4243b86bd0cbfdc5297e2cf36a2fa090"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e975d98d4e0cf4cf3099382376905bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga4e975d98d4e0cf4cf3099382376905bf">XNANDPSU_DMA_SYS_ADDR1_OFFSET</a>&#160;&#160;&#160;0x24U</td></tr>
<tr class="memdesc:ga4e975d98d4e0cf4cf3099382376905bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA System Address 1 Register.  <a href="group__nandpsu__v1__0.html#ga4e975d98d4e0cf4cf3099382376905bf">More...</a><br /></td></tr>
<tr class="separator:ga4e975d98d4e0cf4cf3099382376905bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1a1b5cb5b764c262a5ee379e5bd83162"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1a1b5cb5b764c262a5ee379e5bd83162">XNANDPSU_DMA_BUF_BND_OFFSET</a>&#160;&#160;&#160;0x54U</td></tr>
<tr class="memdesc:ga1a1b5cb5b764c262a5ee379e5bd83162"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Buffer Boundary Register.  <a href="group__nandpsu__v1__0.html#ga1a1b5cb5b764c262a5ee379e5bd83162">More...</a><br /></td></tr>
<tr class="separator:ga1a1b5cb5b764c262a5ee379e5bd83162"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e6f2cce5132af6fb7aded086e100abb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6e6f2cce5132af6fb7aded086e100abb">XNANDPSU_SLV_DMA_CONF_OFFSET</a>&#160;&#160;&#160;0x80U</td></tr>
<tr class="memdesc:ga6e6f2cce5132af6fb7aded086e100abb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave DMA Configuration Register.  <a href="group__nandpsu__v1__0.html#ga6e6f2cce5132af6fb7aded086e100abb">More...</a><br /></td></tr>
<tr class="separator:ga6e6f2cce5132af6fb7aded086e100abb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga541264d14f94a94ef2db439d66eaef00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga541264d14f94a94ef2db439d66eaef00">XNandPsu_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga541264d14f94a94ef2db439d66eaef00"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="group__nandpsu__v1__0.html#ga541264d14f94a94ef2db439d66eaef00">More...</a><br /></td></tr>
<tr class="separator:ga541264d14f94a94ef2db439d66eaef00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13968ef2c371ba365d36cfb05c27d1f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga13968ef2c371ba365d36cfb05c27d1f9">XNandPsu_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td></tr>
<tr class="memdesc:ga13968ef2c371ba365d36cfb05c27d1f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes the given register.  <a href="group__nandpsu__v1__0.html#ga13968ef2c371ba365d36cfb05c27d1f9">More...</a><br /></td></tr>
<tr class="separator:ga13968ef2c371ba365d36cfb05c27d1f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Packet Register bit definitions and masks</div></td></tr>
<tr class="memitem:gaff5a4f3cd89dbc99bfe07ff67fb33bcd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaff5a4f3cd89dbc99bfe07ff67fb33bcd">XNANDPSU_PKT_PKT_SIZE_MASK</a>&#160;&#160;&#160;0x000007FFU</td></tr>
<tr class="memdesc:gaff5a4f3cd89dbc99bfe07ff67fb33bcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Size.  <a href="group__nandpsu__v1__0.html#gaff5a4f3cd89dbc99bfe07ff67fb33bcd">More...</a><br /></td></tr>
<tr class="separator:gaff5a4f3cd89dbc99bfe07ff67fb33bcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae94bec18e6ac1a4a005acc2dcb5bb6ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gae94bec18e6ac1a4a005acc2dcb5bb6ca">XNANDPSU_PKT_PKT_CNT_MASK</a>&#160;&#160;&#160;0x00FFF000U</td></tr>
<tr class="memdesc:gae94bec18e6ac1a4a005acc2dcb5bb6ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count.  <a href="group__nandpsu__v1__0.html#gae94bec18e6ac1a4a005acc2dcb5bb6ca">More...</a><br /></td></tr>
<tr class="separator:gae94bec18e6ac1a4a005acc2dcb5bb6ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7bb914b32ccd8525663a08d8539194e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga7bb914b32ccd8525663a08d8539194e6">XNANDPSU_PKT_PKT_CNT_SHIFT</a>&#160;&#160;&#160;12U</td></tr>
<tr class="memdesc:ga7bb914b32ccd8525663a08d8539194e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count Shift.  <a href="group__nandpsu__v1__0.html#ga7bb914b32ccd8525663a08d8539194e6">More...</a><br /></td></tr>
<tr class="separator:ga7bb914b32ccd8525663a08d8539194e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Memory Address Register 1 bit definitions and masks</div></td></tr>
<tr class="memitem:ga54ddf708eea2b687890ecdba14d03bb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga54ddf708eea2b687890ecdba14d03bb6">XNANDPSU_MEM_ADDR1_COL_ADDR_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga54ddf708eea2b687890ecdba14d03bb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Column Address Mask.  <a href="group__nandpsu__v1__0.html#ga54ddf708eea2b687890ecdba14d03bb6">More...</a><br /></td></tr>
<tr class="separator:ga54ddf708eea2b687890ecdba14d03bb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6eff2647f2f5aa81b257379c2816db0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gab6eff2647f2f5aa81b257379c2816db0">XNANDPSU_MEM_ADDR1_PG_ADDR_MASK</a>&#160;&#160;&#160;0xFFFF0000U</td></tr>
<tr class="memdesc:gab6eff2647f2f5aa81b257379c2816db0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page, Block Address Mask.  <a href="group__nandpsu__v1__0.html#gab6eff2647f2f5aa81b257379c2816db0">More...</a><br /></td></tr>
<tr class="separator:gab6eff2647f2f5aa81b257379c2816db0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac63bb75546ca3b8263c258c51938b282"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gac63bb75546ca3b8263c258c51938b282">XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT</a>&#160;&#160;&#160;16U</td></tr>
<tr class="memdesc:gac63bb75546ca3b8263c258c51938b282"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page Shift.  <a href="group__nandpsu__v1__0.html#gac63bb75546ca3b8263c258c51938b282">More...</a><br /></td></tr>
<tr class="separator:gac63bb75546ca3b8263c258c51938b282"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Memory Address Register 2 bit definitions and masks</div></td></tr>
<tr class="memitem:gaf9f73670a35803702bd1fe6e630523d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf9f73670a35803702bd1fe6e630523d5">XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaf9f73670a35803702bd1fe6e630523d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory Address.  <a href="group__nandpsu__v1__0.html#gaf9f73670a35803702bd1fe6e630523d5">More...</a><br /></td></tr>
<tr class="separator:gaf9f73670a35803702bd1fe6e630523d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d13fe52622748d57ad0951c49ff54fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga9d13fe52622748d57ad0951c49ff54fa">XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK</a>&#160;&#160;&#160;0x01000000U</td></tr>
<tr class="memdesc:ga9d13fe52622748d57ad0951c49ff54fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Width.  <a href="group__nandpsu__v1__0.html#ga9d13fe52622748d57ad0951c49ff54fa">More...</a><br /></td></tr>
<tr class="separator:ga9d13fe52622748d57ad0951c49ff54fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga53497f5949cc23126b7e3190bd3a6908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga53497f5949cc23126b7e3190bd3a6908">XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK</a>&#160;&#160;&#160;0x0E000000U</td></tr>
<tr class="memdesc:ga53497f5949cc23126b7e3190bd3a6908"><td class="mdescLeft">&#160;</td><td class="mdescRight">BCH Mode Value.  <a href="group__nandpsu__v1__0.html#ga53497f5949cc23126b7e3190bd3a6908">More...</a><br /></td></tr>
<tr class="separator:ga53497f5949cc23126b7e3190bd3a6908"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9be27399c2b11f93bb8f2952a162be6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga9be27399c2b11f93bb8f2952a162be6a">XNANDPSU_MEM_ADDR2_MODE_MASK</a>&#160;&#160;&#160;0x30000000U</td></tr>
<tr class="memdesc:ga9be27399c2b11f93bb8f2952a162be6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash Connection Mode.  <a href="group__nandpsu__v1__0.html#ga9be27399c2b11f93bb8f2952a162be6a">More...</a><br /></td></tr>
<tr class="separator:ga9be27399c2b11f93bb8f2952a162be6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gababdf3c8f51458162c74b799162a66fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gababdf3c8f51458162c74b799162a66fe">XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK</a>&#160;&#160;&#160;0xC0000000U</td></tr>
<tr class="memdesc:gababdf3c8f51458162c74b799162a66fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Chip Select.  <a href="group__nandpsu__v1__0.html#gababdf3c8f51458162c74b799162a66fe">More...</a><br /></td></tr>
<tr class="separator:gababdf3c8f51458162c74b799162a66fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ef00be8ac500da3751aea47e8427004"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6ef00be8ac500da3751aea47e8427004">XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT</a>&#160;&#160;&#160;30U</td></tr>
<tr class="memdesc:ga6ef00be8ac500da3751aea47e8427004"><td class="mdescLeft">&#160;</td><td class="mdescRight">Chip select shift.  <a href="group__nandpsu__v1__0.html#ga6ef00be8ac500da3751aea47e8427004">More...</a><br /></td></tr>
<tr class="separator:ga6ef00be8ac500da3751aea47e8427004"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9af3aa809592a351d652abc03746f6b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga9af3aa809592a351d652abc03746f6b4">XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT</a>&#160;&#160;&#160;24U</td></tr>
<tr class="memdesc:ga9af3aa809592a351d652abc03746f6b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus width shift.  <a href="group__nandpsu__v1__0.html#ga9af3aa809592a351d652abc03746f6b4">More...</a><br /></td></tr>
<tr class="separator:ga9af3aa809592a351d652abc03746f6b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b9c9a193fb3b27e3436d2e81e95f26a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT</b>&#160;&#160;&#160;25U</td></tr>
<tr class="separator:ga8b9c9a193fb3b27e3436d2e81e95f26a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Command Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga8be14703559f7520d8a3117232e64c06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga8be14703559f7520d8a3117232e64c06">XNANDPSU_CMD_CMD1_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga8be14703559f7520d8a3117232e64c06"><td class="mdescLeft">&#160;</td><td class="mdescRight">1st Cycle Command  <a href="group__nandpsu__v1__0.html#ga8be14703559f7520d8a3117232e64c06">More...</a><br /></td></tr>
<tr class="separator:ga8be14703559f7520d8a3117232e64c06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacadb4a6cbb11dd64c3d6be90a5ccf820"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gacadb4a6cbb11dd64c3d6be90a5ccf820">XNANDPSU_CMD_CMD2_MASK</a>&#160;&#160;&#160;0x0000FF00U</td></tr>
<tr class="memdesc:gacadb4a6cbb11dd64c3d6be90a5ccf820"><td class="mdescLeft">&#160;</td><td class="mdescRight">2nd Cycle Command  <a href="group__nandpsu__v1__0.html#gacadb4a6cbb11dd64c3d6be90a5ccf820">More...</a><br /></td></tr>
<tr class="separator:gacadb4a6cbb11dd64c3d6be90a5ccf820"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e360fc42464429db754164c281e833f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6e360fc42464429db754164c281e833f">XNANDPSU_CMD_PG_SIZE_MASK</a>&#160;&#160;&#160;0x03800000U</td></tr>
<tr class="memdesc:ga6e360fc42464429db754164c281e833f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page Size.  <a href="group__nandpsu__v1__0.html#ga6e360fc42464429db754164c281e833f">More...</a><br /></td></tr>
<tr class="separator:ga6e360fc42464429db754164c281e833f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1165fe99133cfe6c3c3f6dea1bddd81d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1165fe99133cfe6c3c3f6dea1bddd81d">XNANDPSU_CMD_DMA_EN_MASK</a>&#160;&#160;&#160;0x0C000000U</td></tr>
<tr class="memdesc:ga1165fe99133cfe6c3c3f6dea1bddd81d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Enable Mode.  <a href="group__nandpsu__v1__0.html#ga1165fe99133cfe6c3c3f6dea1bddd81d">More...</a><br /></td></tr>
<tr class="separator:ga1165fe99133cfe6c3c3f6dea1bddd81d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1b6a2ad4deb045b9ecb3e2309438585"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa1b6a2ad4deb045b9ecb3e2309438585">XNANDPSU_CMD_ADDR_CYCLES_MASK</a>&#160;&#160;&#160;0x70000000U</td></tr>
<tr class="memdesc:gaa1b6a2ad4deb045b9ecb3e2309438585"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Address Cycles.  <a href="group__nandpsu__v1__0.html#gaa1b6a2ad4deb045b9ecb3e2309438585">More...</a><br /></td></tr>
<tr class="separator:gaa1b6a2ad4deb045b9ecb3e2309438585"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae9d4edc9daf720b8a6dd430b1b41037e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gae9d4edc9daf720b8a6dd430b1b41037e">XNANDPSU_CMD_ECC_ON_MASK</a>&#160;&#160;&#160;0x80000000U</td></tr>
<tr class="memdesc:gae9d4edc9daf720b8a6dd430b1b41037e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC ON/OFF.  <a href="group__nandpsu__v1__0.html#gae9d4edc9daf720b8a6dd430b1b41037e">More...</a><br /></td></tr>
<tr class="separator:gae9d4edc9daf720b8a6dd430b1b41037e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga548e02649547dbb26d3ba373b67a185a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga548e02649547dbb26d3ba373b67a185a">XNANDPSU_CMD_CMD2_SHIFT</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:ga548e02649547dbb26d3ba373b67a185a"><td class="mdescLeft">&#160;</td><td class="mdescRight">2nd Cycle Command Shift  <a href="group__nandpsu__v1__0.html#ga548e02649547dbb26d3ba373b67a185a">More...</a><br /></td></tr>
<tr class="separator:ga548e02649547dbb26d3ba373b67a185a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d66adb5ed5172971ccd6133e493ee45"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga7d66adb5ed5172971ccd6133e493ee45">XNANDPSU_CMD_PG_SIZE_SHIFT</a>&#160;&#160;&#160;23U</td></tr>
<tr class="memdesc:ga7d66adb5ed5172971ccd6133e493ee45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page Size Shift.  <a href="group__nandpsu__v1__0.html#ga7d66adb5ed5172971ccd6133e493ee45">More...</a><br /></td></tr>
<tr class="separator:ga7d66adb5ed5172971ccd6133e493ee45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31cd55caad2584c9d1dcf333c526e7ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga31cd55caad2584c9d1dcf333c526e7ca">XNANDPSU_CMD_DMA_EN_SHIFT</a>&#160;&#160;&#160;26U</td></tr>
<tr class="memdesc:ga31cd55caad2584c9d1dcf333c526e7ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Enable Shift.  <a href="group__nandpsu__v1__0.html#ga31cd55caad2584c9d1dcf333c526e7ca">More...</a><br /></td></tr>
<tr class="separator:ga31cd55caad2584c9d1dcf333c526e7ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4289b87f7c202422ab0c90fe284d759e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga4289b87f7c202422ab0c90fe284d759e">XNANDPSU_CMD_ADDR_CYCLES_SHIFT</a>&#160;&#160;&#160;28U</td></tr>
<tr class="memdesc:ga4289b87f7c202422ab0c90fe284d759e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Address Cycles Shift.  <a href="group__nandpsu__v1__0.html#ga4289b87f7c202422ab0c90fe284d759e">More...</a><br /></td></tr>
<tr class="separator:ga4289b87f7c202422ab0c90fe284d759e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga390ead6fc832b4423d5769094880951f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga390ead6fc832b4423d5769094880951f">XNANDPSU_CMD_ECC_ON_SHIFT</a>&#160;&#160;&#160;31U</td></tr>
<tr class="memdesc:ga390ead6fc832b4423d5769094880951f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC ON/OFF.  <a href="group__nandpsu__v1__0.html#ga390ead6fc832b4423d5769094880951f">More...</a><br /></td></tr>
<tr class="separator:ga390ead6fc832b4423d5769094880951f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Program Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga3c38a395e56cd70c7c6bb4cba7b31d43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga3c38a395e56cd70c7c6bb4cba7b31d43">XNANDPSU_PROG_RD_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga3c38a395e56cd70c7c6bb4cba7b31d43"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read.  <a href="group__nandpsu__v1__0.html#ga3c38a395e56cd70c7c6bb4cba7b31d43">More...</a><br /></td></tr>
<tr class="separator:ga3c38a395e56cd70c7c6bb4cba7b31d43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e62fd307ad3929f6bd3cadfe6042e23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1e62fd307ad3929f6bd3cadfe6042e23">XNANDPSU_PROG_MUL_DIE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga1e62fd307ad3929f6bd3cadfe6042e23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Die.  <a href="group__nandpsu__v1__0.html#ga1e62fd307ad3929f6bd3cadfe6042e23">More...</a><br /></td></tr>
<tr class="separator:ga1e62fd307ad3929f6bd3cadfe6042e23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga438b57de344713f8444fcd11496d1098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga438b57de344713f8444fcd11496d1098">XNANDPSU_PROG_BLK_ERASE_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga438b57de344713f8444fcd11496d1098"><td class="mdescLeft">&#160;</td><td class="mdescRight">Block Erase.  <a href="group__nandpsu__v1__0.html#ga438b57de344713f8444fcd11496d1098">More...</a><br /></td></tr>
<tr class="separator:ga438b57de344713f8444fcd11496d1098"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81d41547ab7fd4a73c30439f12f7d4b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga81d41547ab7fd4a73c30439f12f7d4b4">XNANDPSU_PROG_RD_STS_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga81d41547ab7fd4a73c30439f12f7d4b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Status.  <a href="group__nandpsu__v1__0.html#ga81d41547ab7fd4a73c30439f12f7d4b4">More...</a><br /></td></tr>
<tr class="separator:ga81d41547ab7fd4a73c30439f12f7d4b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8283bf247a2fdc39f13634b42da12938"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga8283bf247a2fdc39f13634b42da12938">XNANDPSU_PROG_PG_PROG_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga8283bf247a2fdc39f13634b42da12938"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page Program.  <a href="group__nandpsu__v1__0.html#ga8283bf247a2fdc39f13634b42da12938">More...</a><br /></td></tr>
<tr class="separator:ga8283bf247a2fdc39f13634b42da12938"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4ebdac84eff62e4c0acb55178e58ae6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga4ebdac84eff62e4c0acb55178e58ae6f">XNANDPSU_PROG_MUL_DIE_RD_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:ga4ebdac84eff62e4c0acb55178e58ae6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Die Rd.  <a href="group__nandpsu__v1__0.html#ga4ebdac84eff62e4c0acb55178e58ae6f">More...</a><br /></td></tr>
<tr class="separator:ga4ebdac84eff62e4c0acb55178e58ae6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga174d9c67daa7ee1eb90f9527b8e944f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga174d9c67daa7ee1eb90f9527b8e944f7">XNANDPSU_PROG_RD_ID_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga174d9c67daa7ee1eb90f9527b8e944f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read ID.  <a href="group__nandpsu__v1__0.html#ga174d9c67daa7ee1eb90f9527b8e944f7">More...</a><br /></td></tr>
<tr class="separator:ga174d9c67daa7ee1eb90f9527b8e944f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09ec25683ecf1c52b4386aec2c56e799"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga09ec25683ecf1c52b4386aec2c56e799">XNANDPSU_PROG_RD_PRM_PG_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga09ec25683ecf1c52b4386aec2c56e799"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Param Page.  <a href="group__nandpsu__v1__0.html#ga09ec25683ecf1c52b4386aec2c56e799">More...</a><br /></td></tr>
<tr class="separator:ga09ec25683ecf1c52b4386aec2c56e799"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9db90a714c444e48f2837a6550baf03b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga9db90a714c444e48f2837a6550baf03b">XNANDPSU_PROG_RST_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga9db90a714c444e48f2837a6550baf03b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset.  <a href="group__nandpsu__v1__0.html#ga9db90a714c444e48f2837a6550baf03b">More...</a><br /></td></tr>
<tr class="separator:ga9db90a714c444e48f2837a6550baf03b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6db393ae018d58368f3fff85591c84fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6db393ae018d58368f3fff85591c84fe">XNANDPSU_PROG_GET_FEATURES_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga6db393ae018d58368f3fff85591c84fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Features.  <a href="group__nandpsu__v1__0.html#ga6db393ae018d58368f3fff85591c84fe">More...</a><br /></td></tr>
<tr class="separator:ga6db393ae018d58368f3fff85591c84fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf472233e7c587746e007d035d5c6807"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gadf472233e7c587746e007d035d5c6807">XNANDPSU_PROG_SET_FEATURES_MASK</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:gadf472233e7c587746e007d035d5c6807"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set Features.  <a href="group__nandpsu__v1__0.html#gadf472233e7c587746e007d035d5c6807">More...</a><br /></td></tr>
<tr class="separator:gadf472233e7c587746e007d035d5c6807"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabda8fb5fcc322128f76db97b6d83a64d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gabda8fb5fcc322128f76db97b6d83a64d">XNANDPSU_PROG_RD_UNQ_ID_MASK</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:gabda8fb5fcc322128f76db97b6d83a64d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Unique ID.  <a href="group__nandpsu__v1__0.html#gabda8fb5fcc322128f76db97b6d83a64d">More...</a><br /></td></tr>
<tr class="separator:gabda8fb5fcc322128f76db97b6d83a64d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7739734fff8dd0b231b2b1b617fde0a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga7739734fff8dd0b231b2b1b617fde0a4">XNANDPSU_PROG_RD_STS_ENH_MASK</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:ga7739734fff8dd0b231b2b1b617fde0a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Status Enhanced.  <a href="group__nandpsu__v1__0.html#ga7739734fff8dd0b231b2b1b617fde0a4">More...</a><br /></td></tr>
<tr class="separator:ga7739734fff8dd0b231b2b1b617fde0a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c9ef1217ed97793344622228e3107a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga2c9ef1217ed97793344622228e3107a6">XNANDPSU_PROG_RD_INTRLVD_MASK</a>&#160;&#160;&#160;0x00002000U</td></tr>
<tr class="memdesc:ga2c9ef1217ed97793344622228e3107a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Interleaved.  <a href="group__nandpsu__v1__0.html#ga2c9ef1217ed97793344622228e3107a6">More...</a><br /></td></tr>
<tr class="separator:ga2c9ef1217ed97793344622228e3107a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadf5933321faab54c9b4a9745b2c0288"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaadf5933321faab54c9b4a9745b2c0288">XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:gaadf5933321faab54c9b4a9745b2c0288"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change Read Column Enhanced.  <a href="group__nandpsu__v1__0.html#gaadf5933321faab54c9b4a9745b2c0288">More...</a><br /></td></tr>
<tr class="separator:gaadf5933321faab54c9b4a9745b2c0288"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1218c07eb4ca421ebebe66ad437e70f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gab1218c07eb4ca421ebebe66ad437e70f">XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:gab1218c07eb4ca421ebebe66ad437e70f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Copy Back Interleaved.  <a href="group__nandpsu__v1__0.html#gab1218c07eb4ca421ebebe66ad437e70f">More...</a><br /></td></tr>
<tr class="separator:gab1218c07eb4ca421ebebe66ad437e70f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb66fdf840870fec5f181204179e3f1a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaeb66fdf840870fec5f181204179e3f1a">XNANDPSU_PROG_RD_CACHE_START_MASK</a>&#160;&#160;&#160;0x00010000U</td></tr>
<tr class="memdesc:gaeb66fdf840870fec5f181204179e3f1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Cache Start.  <a href="group__nandpsu__v1__0.html#gaeb66fdf840870fec5f181204179e3f1a">More...</a><br /></td></tr>
<tr class="separator:gaeb66fdf840870fec5f181204179e3f1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6418bbc8604bf65ebe368fe07a0fa891"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6418bbc8604bf65ebe368fe07a0fa891">XNANDPSU_PROG_RD_CACHE_SEQ_MASK</a>&#160;&#160;&#160;0x00020000U</td></tr>
<tr class="memdesc:ga6418bbc8604bf65ebe368fe07a0fa891"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Cache Sequential.  <a href="group__nandpsu__v1__0.html#ga6418bbc8604bf65ebe368fe07a0fa891">More...</a><br /></td></tr>
<tr class="separator:ga6418bbc8604bf65ebe368fe07a0fa891"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1126f95d5a98b2375d0266c6db3e92e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1126f95d5a98b2375d0266c6db3e92e5">XNANDPSU_PROG_RD_CACHE_RAND_MASK</a>&#160;&#160;&#160;0x00040000U</td></tr>
<tr class="memdesc:ga1126f95d5a98b2375d0266c6db3e92e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Cache Random.  <a href="group__nandpsu__v1__0.html#ga1126f95d5a98b2375d0266c6db3e92e5">More...</a><br /></td></tr>
<tr class="separator:ga1126f95d5a98b2375d0266c6db3e92e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8166724a7206cd0c5564f97977ff444e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga8166724a7206cd0c5564f97977ff444e">XNANDPSU_PROG_RD_CACHE_END_MASK</a>&#160;&#160;&#160;0x00080000U</td></tr>
<tr class="memdesc:ga8166724a7206cd0c5564f97977ff444e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Cache End.  <a href="group__nandpsu__v1__0.html#ga8166724a7206cd0c5564f97977ff444e">More...</a><br /></td></tr>
<tr class="separator:ga8166724a7206cd0c5564f97977ff444e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca5b1533ad5ea4b17b9a932221c3189a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaca5b1533ad5ea4b17b9a932221c3189a">XNANDPSU_PROG_SMALL_DATA_MOVE_MASK</a>&#160;&#160;&#160;0x00100000U</td></tr>
<tr class="memdesc:gaca5b1533ad5ea4b17b9a932221c3189a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Small Data Move.  <a href="group__nandpsu__v1__0.html#gaca5b1533ad5ea4b17b9a932221c3189a">More...</a><br /></td></tr>
<tr class="separator:gaca5b1533ad5ea4b17b9a932221c3189a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf52a34b9e6851425cef6986b01daf7d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf52a34b9e6851425cef6986b01daf7d7">XNANDPSU_PROG_CHNG_ROW_ADDR_MASK</a>&#160;&#160;&#160;0x00200000U</td></tr>
<tr class="memdesc:gaf52a34b9e6851425cef6986b01daf7d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change Row Address.  <a href="group__nandpsu__v1__0.html#gaf52a34b9e6851425cef6986b01daf7d7">More...</a><br /></td></tr>
<tr class="separator:gaf52a34b9e6851425cef6986b01daf7d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd3c66bd83d79ea5e89a220e4459a121"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gafd3c66bd83d79ea5e89a220e4459a121">XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK</a>&#160;&#160;&#160;0x00400000U</td></tr>
<tr class="memdesc:gafd3c66bd83d79ea5e89a220e4459a121"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change Row Address End.  <a href="group__nandpsu__v1__0.html#gafd3c66bd83d79ea5e89a220e4459a121">More...</a><br /></td></tr>
<tr class="separator:gafd3c66bd83d79ea5e89a220e4459a121"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7420ae607c46fc1a461eaad42b5310cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga7420ae607c46fc1a461eaad42b5310cc">XNANDPSU_PROG_RST_LUN_MASK</a>&#160;&#160;&#160;0x00800000U</td></tr>
<tr class="memdesc:ga7420ae607c46fc1a461eaad42b5310cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset LUN.  <a href="group__nandpsu__v1__0.html#ga7420ae607c46fc1a461eaad42b5310cc">More...</a><br /></td></tr>
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<tr class="memitem:gaa789076d269cb48b93e89cf3c7f82719"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa789076d269cb48b93e89cf3c7f82719">XNANDPSU_PROG_PGM_PG_CLR_MASK</a>&#160;&#160;&#160;0x01000000U</td></tr>
<tr class="memdesc:gaa789076d269cb48b93e89cf3c7f82719"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enhanced Program Page Register Clear.  <a href="group__nandpsu__v1__0.html#gaa789076d269cb48b93e89cf3c7f82719">More...</a><br /></td></tr>
<tr class="separator:gaa789076d269cb48b93e89cf3c7f82719"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff674fd5d8a065adfa37d2c284deee88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaff674fd5d8a065adfa37d2c284deee88">XNANDPSU_PROG_VOL_SEL_MASK</a>&#160;&#160;&#160;0x02000000U</td></tr>
<tr class="memdesc:gaff674fd5d8a065adfa37d2c284deee88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Volume Select.  <a href="group__nandpsu__v1__0.html#gaff674fd5d8a065adfa37d2c284deee88">More...</a><br /></td></tr>
<tr class="separator:gaff674fd5d8a065adfa37d2c284deee88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaccbe018ae70ca6e190c73e8c2b7ca0d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaccbe018ae70ca6e190c73e8c2b7ca0d8">XNANDPSU_PROG_ODT_CONF_MASK</a>&#160;&#160;&#160;0x04000000U</td></tr>
<tr class="memdesc:gaccbe018ae70ca6e190c73e8c2b7ca0d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ODT Configure.  <a href="group__nandpsu__v1__0.html#gaccbe018ae70ca6e190c73e8c2b7ca0d8">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Status Enable Register bit definitions and masks</div></td></tr>
<tr class="memitem:gafb9c672287fcc76bbb63e86e04c596ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gafb9c672287fcc76bbb63e86e04c596ac">XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gafb9c672287fcc76bbb63e86e04c596ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Write Ready Status Enable.  <a href="group__nandpsu__v1__0.html#gafb9c672287fcc76bbb63e86e04c596ac">More...</a><br /></td></tr>
<tr class="separator:gafb9c672287fcc76bbb63e86e04c596ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga145b9b3fbd465190f747e8fb3ff1935a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga145b9b3fbd465190f747e8fb3ff1935a">XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga145b9b3fbd465190f747e8fb3ff1935a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Read Ready Status Enable.  <a href="group__nandpsu__v1__0.html#ga145b9b3fbd465190f747e8fb3ff1935a">More...</a><br /></td></tr>
<tr class="separator:ga145b9b3fbd465190f747e8fb3ff1935a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad19965121768bf4ada7285e14ad831a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gad19965121768bf4ada7285e14ad831a0">XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gad19965121768bf4ada7285e14ad831a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Complete Status Enable.  <a href="group__nandpsu__v1__0.html#gad19965121768bf4ada7285e14ad831a0">More...</a><br /></td></tr>
<tr class="separator:gad19965121768bf4ada7285e14ad831a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga225e3c2c1e47f366e201862df3f2a425"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga225e3c2c1e47f366e201862df3f2a425">XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga225e3c2c1e47f366e201862df3f2a425"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Bit Error Status Enable.  <a href="group__nandpsu__v1__0.html#ga225e3c2c1e47f366e201862df3f2a425">More...</a><br /></td></tr>
<tr class="separator:ga225e3c2c1e47f366e201862df3f2a425"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18cc911e7b742c86aca0cd41427f5709"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga18cc911e7b742c86aca0cd41427f5709">XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga18cc911e7b742c86aca0cd41427f5709"><td class="mdescLeft">&#160;</td><td class="mdescRight">Single Bit Error Status Enable, BCH Detect Error Status Enable.  <a href="group__nandpsu__v1__0.html#ga18cc911e7b742c86aca0cd41427f5709">More...</a><br /></td></tr>
<tr class="separator:ga18cc911e7b742c86aca0cd41427f5709"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b8ba65fd47a9bcc532ddd420600be16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1b8ba65fd47a9bcc532ddd420600be16">XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga1b8ba65fd47a9bcc532ddd420600be16"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Status Enable.  <a href="group__nandpsu__v1__0.html#ga1b8ba65fd47a9bcc532ddd420600be16">More...</a><br /></td></tr>
<tr class="separator:ga1b8ba65fd47a9bcc532ddd420600be16"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4991de46bf5054ac551c643f601ac985"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga4991de46bf5054ac551c643f601ac985">XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga4991de46bf5054ac551c643f601ac985"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error AHB Status Enable.  <a href="group__nandpsu__v1__0.html#ga4991de46bf5054ac551c643f601ac985">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Signal Enable Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga1992e66b7033b24922ed9ceadd0246b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1992e66b7033b24922ed9ceadd0246b1">XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga1992e66b7033b24922ed9ceadd0246b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Write Ready Signal Enable.  <a href="group__nandpsu__v1__0.html#ga1992e66b7033b24922ed9ceadd0246b1">More...</a><br /></td></tr>
<tr class="separator:ga1992e66b7033b24922ed9ceadd0246b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3f422c1d70ba95d7192e18ff0d2ccdd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa3f422c1d70ba95d7192e18ff0d2ccdd">XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa3f422c1d70ba95d7192e18ff0d2ccdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Read Ready Signal Enable.  <a href="group__nandpsu__v1__0.html#gaa3f422c1d70ba95d7192e18ff0d2ccdd">More...</a><br /></td></tr>
<tr class="separator:gaa3f422c1d70ba95d7192e18ff0d2ccdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec9d3570d2544d2538356983fbc93aef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaec9d3570d2544d2538356983fbc93aef">XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gaec9d3570d2544d2538356983fbc93aef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Complete Signal Enable.  <a href="group__nandpsu__v1__0.html#gaec9d3570d2544d2538356983fbc93aef">More...</a><br /></td></tr>
<tr class="separator:gaec9d3570d2544d2538356983fbc93aef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaccf834d31e334684f1c3edc2ba85ed4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaccf834d31e334684f1c3edc2ba85ed4b">XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaccf834d31e334684f1c3edc2ba85ed4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Bit Error Signal Enable.  <a href="group__nandpsu__v1__0.html#gaccf834d31e334684f1c3edc2ba85ed4b">More...</a><br /></td></tr>
<tr class="separator:gaccf834d31e334684f1c3edc2ba85ed4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4793212af4be840c53cc4fd5100809f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gac4793212af4be840c53cc4fd5100809f">XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gac4793212af4be840c53cc4fd5100809f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Single Bit Error Signal Enable, BCH Detect Error Signal Enable.  <a href="group__nandpsu__v1__0.html#gac4793212af4be840c53cc4fd5100809f">More...</a><br /></td></tr>
<tr class="separator:gac4793212af4be840c53cc4fd5100809f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0f1a8eb12f60f4bcb62e80fa5ea1427"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf0f1a8eb12f60f4bcb62e80fa5ea1427">XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gaf0f1a8eb12f60f4bcb62e80fa5ea1427"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Signal Enable.  <a href="group__nandpsu__v1__0.html#gaf0f1a8eb12f60f4bcb62e80fa5ea1427">More...</a><br /></td></tr>
<tr class="separator:gaf0f1a8eb12f60f4bcb62e80fa5ea1427"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cab16ebdaea1fa3b25b94c4a38faa2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6cab16ebdaea1fa3b25b94c4a38faa2f">XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga6cab16ebdaea1fa3b25b94c4a38faa2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error AHB Signal Enable.  <a href="group__nandpsu__v1__0.html#ga6cab16ebdaea1fa3b25b94c4a38faa2f">More...</a><br /></td></tr>
<tr class="separator:ga6cab16ebdaea1fa3b25b94c4a38faa2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Status Register bit definitions and masks</div></td></tr>
<tr class="memitem:gae62e6f19f413fd5a342a6bad4109a14c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gae62e6f19f413fd5a342a6bad4109a14c">XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gae62e6f19f413fd5a342a6bad4109a14c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Write Ready.  <a href="group__nandpsu__v1__0.html#gae62e6f19f413fd5a342a6bad4109a14c">More...</a><br /></td></tr>
<tr class="separator:gae62e6f19f413fd5a342a6bad4109a14c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5bb4ebb8858c80a0fbc70bc9ec1c8c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa5bb4ebb8858c80a0fbc70bc9ec1c8c4">XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa5bb4ebb8858c80a0fbc70bc9ec1c8c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Read Ready.  <a href="group__nandpsu__v1__0.html#gaa5bb4ebb8858c80a0fbc70bc9ec1c8c4">More...</a><br /></td></tr>
<tr class="separator:gaa5bb4ebb8858c80a0fbc70bc9ec1c8c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97422ad3a8c3a3467e9690f34c2d4b6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga97422ad3a8c3a3467e9690f34c2d4b6d">XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga97422ad3a8c3a3467e9690f34c2d4b6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Complete.  <a href="group__nandpsu__v1__0.html#ga97422ad3a8c3a3467e9690f34c2d4b6d">More...</a><br /></td></tr>
<tr class="separator:ga97422ad3a8c3a3467e9690f34c2d4b6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc22839b9c591d69f1c8d493e846cb5f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gacc22839b9c591d69f1c8d493e846cb5f">XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gacc22839b9c591d69f1c8d493e846cb5f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Bit Error.  <a href="group__nandpsu__v1__0.html#gacc22839b9c591d69f1c8d493e846cb5f">More...</a><br /></td></tr>
<tr class="separator:gacc22839b9c591d69f1c8d493e846cb5f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55a21ebd02928d9a6ad5cde4921518a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga55a21ebd02928d9a6ad5cde4921518a0">XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga55a21ebd02928d9a6ad5cde4921518a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Single Bit Error, BCH Detect Error.  <a href="group__nandpsu__v1__0.html#ga55a21ebd02928d9a6ad5cde4921518a0">More...</a><br /></td></tr>
<tr class="separator:ga55a21ebd02928d9a6ad5cde4921518a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80a79e28e9cd6a7578ca9acb05f887c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga80a79e28e9cd6a7578ca9acb05f887c5">XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga80a79e28e9cd6a7578ca9acb05f887c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Interrupt.  <a href="group__nandpsu__v1__0.html#ga80a79e28e9cd6a7578ca9acb05f887c5">More...</a><br /></td></tr>
<tr class="separator:ga80a79e28e9cd6a7578ca9acb05f887c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89851ad93665e6d0f4cda642cd0b29f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga89851ad93665e6d0f4cda642cd0b29f4">XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:ga89851ad93665e6d0f4cda642cd0b29f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error AHB.  <a href="group__nandpsu__v1__0.html#ga89851ad93665e6d0f4cda642cd0b29f4">More...</a><br /></td></tr>
<tr class="separator:ga89851ad93665e6d0f4cda642cd0b29f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt bit definitions and masks</div></td></tr>
<tr class="memitem:ga1a2ebef7b0dce3076218b70769c9dd4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga1a2ebef7b0dce3076218b70769c9dd4e">XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga1a2ebef7b0dce3076218b70769c9dd4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Write Ready Status Enable.  <a href="group__nandpsu__v1__0.html#ga1a2ebef7b0dce3076218b70769c9dd4e">More...</a><br /></td></tr>
<tr class="separator:ga1a2ebef7b0dce3076218b70769c9dd4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6e729c0707474c208d2d53fd8f4d78b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf6e729c0707474c208d2d53fd8f4d78b">XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaf6e729c0707474c208d2d53fd8f4d78b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer Read Ready Status Enable.  <a href="group__nandpsu__v1__0.html#gaf6e729c0707474c208d2d53fd8f4d78b">More...</a><br /></td></tr>
<tr class="separator:gaf6e729c0707474c208d2d53fd8f4d78b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90c8386b1051e1a22edbd499e22277d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga90c8386b1051e1a22edbd499e22277d3">XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga90c8386b1051e1a22edbd499e22277d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Complete Status Enable.  <a href="group__nandpsu__v1__0.html#ga90c8386b1051e1a22edbd499e22277d3">More...</a><br /></td></tr>
<tr class="separator:ga90c8386b1051e1a22edbd499e22277d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00080c00cd52f8d759207f46da1812e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga00080c00cd52f8d759207f46da1812e6">XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga00080c00cd52f8d759207f46da1812e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multi Bit Error Status Enable.  <a href="group__nandpsu__v1__0.html#ga00080c00cd52f8d759207f46da1812e6">More...</a><br /></td></tr>
<tr class="separator:ga00080c00cd52f8d759207f46da1812e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafae759a24262ac1abeef7f21b4588537"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gafae759a24262ac1abeef7f21b4588537">XNANDPSU_INTR_ERR_INTR_STS_EN_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gafae759a24262ac1abeef7f21b4588537"><td class="mdescLeft">&#160;</td><td class="mdescRight">Single Bit Error Status Enable, BCH Detect Error Status Enable.  <a href="group__nandpsu__v1__0.html#gafae759a24262ac1abeef7f21b4588537">More...</a><br /></td></tr>
<tr class="separator:gafae759a24262ac1abeef7f21b4588537"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5bb73feb9da2cd28883dd8791505a9d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga5bb73feb9da2cd28883dd8791505a9d3">XNANDPSU_INTR_DMA_INT_STS_EN_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga5bb73feb9da2cd28883dd8791505a9d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Status Enable.  <a href="group__nandpsu__v1__0.html#ga5bb73feb9da2cd28883dd8791505a9d3">More...</a><br /></td></tr>
<tr class="separator:ga5bb73feb9da2cd28883dd8791505a9d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8453a8e2c46bbe91ea858c0733d547a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaf8453a8e2c46bbe91ea858c0733d547a">XNANDPSU_INTR_ERR_AHB_STS_EN_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gaf8453a8e2c46bbe91ea858c0733d547a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error AHB Status Enable.  <a href="group__nandpsu__v1__0.html#gaf8453a8e2c46bbe91ea858c0733d547a">More...</a><br /></td></tr>
<tr class="separator:gaf8453a8e2c46bbe91ea858c0733d547a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ID2 Register bit definitions and masks</div></td></tr>
<tr class="memitem:gacd278344026a53c088f8e57e15e10b4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gacd278344026a53c088f8e57e15e10b4e">XNANDPSU_ID2_DEVICE_ID2_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gacd278344026a53c088f8e57e15e10b4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSB Device ID.  <a href="group__nandpsu__v1__0.html#gacd278344026a53c088f8e57e15e10b4e">More...</a><br /></td></tr>
<tr class="separator:gacd278344026a53c088f8e57e15e10b4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Flash Status Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga50e271f7688c49f944f5fdd11a28008a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga50e271f7688c49f944f5fdd11a28008a">XNANDPSU_FLASH_STS_FLASH_STS_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:ga50e271f7688c49f944f5fdd11a28008a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash Status Value.  <a href="group__nandpsu__v1__0.html#ga50e271f7688c49f944f5fdd11a28008a">More...</a><br /></td></tr>
<tr class="separator:ga50e271f7688c49f944f5fdd11a28008a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Timing Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga6654ac2cca76bc95aca0a3612fe3b435"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga6654ac2cca76bc95aca0a3612fe3b435">XNANDPSU_TIMING_TCCS_TIME_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga6654ac2cca76bc95aca0a3612fe3b435"><td class="mdescLeft">&#160;</td><td class="mdescRight">Change column setup time.  <a href="group__nandpsu__v1__0.html#ga6654ac2cca76bc95aca0a3612fe3b435">More...</a><br /></td></tr>
<tr class="separator:ga6654ac2cca76bc95aca0a3612fe3b435"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06d45acea908c6857ef14851bd5e9c63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga06d45acea908c6857ef14851bd5e9c63">XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga06d45acea908c6857ef14851bd5e9c63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slow/Fast device.  <a href="group__nandpsu__v1__0.html#ga06d45acea908c6857ef14851bd5e9c63">More...</a><br /></td></tr>
<tr class="separator:ga06d45acea908c6857ef14851bd5e9c63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf007d0dffc14a704592683dff2ca981"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gacf007d0dffc14a704592683dff2ca981">XNANDPSU_TIMING_DQS_BUFF_SEL_MASK</a>&#160;&#160;&#160;0x00000078U</td></tr>
<tr class="memdesc:gacf007d0dffc14a704592683dff2ca981"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write/Read data transaction value.  <a href="group__nandpsu__v1__0.html#gacf007d0dffc14a704592683dff2ca981">More...</a><br /></td></tr>
<tr class="separator:gacf007d0dffc14a704592683dff2ca981"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a8d1587d7dc738a35c3ec367b605a92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga5a8d1587d7dc738a35c3ec367b605a92">XNANDPSU_TIMING_TADL_TIME_MASK</a>&#160;&#160;&#160;0x00007F80U</td></tr>
<tr class="memdesc:ga5a8d1587d7dc738a35c3ec367b605a92"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address latch enable to Data loading time.  <a href="group__nandpsu__v1__0.html#ga5a8d1587d7dc738a35c3ec367b605a92">More...</a><br /></td></tr>
<tr class="separator:ga5a8d1587d7dc738a35c3ec367b605a92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ECC Register bit definitions and masks</div></td></tr>
<tr class="memitem:gaa15d3fa3bf04e12027240dd40fa6dfc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa15d3fa3bf04e12027240dd40fa6dfc1">XNANDPSU_ECC_ADDR_MASK</a>&#160;&#160;&#160;0x0000FFFFU</td></tr>
<tr class="memdesc:gaa15d3fa3bf04e12027240dd40fa6dfc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC address.  <a href="group__nandpsu__v1__0.html#gaa15d3fa3bf04e12027240dd40fa6dfc1">More...</a><br /></td></tr>
<tr class="separator:gaa15d3fa3bf04e12027240dd40fa6dfc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd72b80bb40b06903b297413e34dd1c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gabd72b80bb40b06903b297413e34dd1c0">XNANDPSU_ECC_SIZE_MASK</a>&#160;&#160;&#160;0x01FF0000U</td></tr>
<tr class="memdesc:gabd72b80bb40b06903b297413e34dd1c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC size.  <a href="group__nandpsu__v1__0.html#gabd72b80bb40b06903b297413e34dd1c0">More...</a><br /></td></tr>
<tr class="separator:gabd72b80bb40b06903b297413e34dd1c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e4296f9673030022b7a75c12fec561e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga3e4296f9673030022b7a75c12fec561e">XNANDPSU_ECC_HAMMING_BCH_MASK</a>&#160;&#160;&#160;0x02000000U</td></tr>
<tr class="memdesc:ga3e4296f9673030022b7a75c12fec561e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hamming/BCH support.  <a href="group__nandpsu__v1__0.html#ga3e4296f9673030022b7a75c12fec561e">More...</a><br /></td></tr>
<tr class="separator:ga3e4296f9673030022b7a75c12fec561e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ECC Error Count Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga620d7a1db0f858f953768fe5529dd0fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga620d7a1db0f858f953768fe5529dd0fe">XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga620d7a1db0f858f953768fe5529dd0fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet bound error count.  <a href="group__nandpsu__v1__0.html#ga620d7a1db0f858f953768fe5529dd0fe">More...</a><br /></td></tr>
<tr class="separator:ga620d7a1db0f858f953768fe5529dd0fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa4b650601243772063b53a755fb91e5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gaa4b650601243772063b53a755fb91e5b">XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK</a>&#160;&#160;&#160;0x0000FF00U</td></tr>
<tr class="memdesc:gaa4b650601243772063b53a755fb91e5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Page bound error count.  <a href="group__nandpsu__v1__0.html#gaa4b650601243772063b53a755fb91e5b">More...</a><br /></td></tr>
<tr class="separator:gaa4b650601243772063b53a755fb91e5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ECC Spare Command Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga50abec7f8c788073e486877a8734c58e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga50abec7f8c788073e486877a8734c58e">XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga50abec7f8c788073e486877a8734c58e"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECC spare command.  <a href="group__nandpsu__v1__0.html#ga50abec7f8c788073e486877a8734c58e">More...</a><br /></td></tr>
<tr class="separator:ga50abec7f8c788073e486877a8734c58e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga71944613f55039e041250518447d300a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga71944613f55039e041250518447d300a">XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK</a>&#160;&#160;&#160;0x70000000U</td></tr>
<tr class="memdesc:ga71944613f55039e041250518447d300a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of ECC/ spare address cycles.  <a href="group__nandpsu__v1__0.html#ga71944613f55039e041250518447d300a">More...</a><br /></td></tr>
<tr class="separator:ga71944613f55039e041250518447d300a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Interface Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga0814a2358814f9ecd61b675a3b05a3e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga0814a2358814f9ecd61b675a3b05a3e6">XNANDPSU_DATA_INTF_SDR_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga0814a2358814f9ecd61b675a3b05a3e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDR mode.  <a href="group__nandpsu__v1__0.html#ga0814a2358814f9ecd61b675a3b05a3e6">More...</a><br /></td></tr>
<tr class="separator:ga0814a2358814f9ecd61b675a3b05a3e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2af319aa44c2289c2ad189f85adc64af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga2af319aa44c2289c2ad189f85adc64af">XNANDPSU_DATA_INTF_NVDDR_MASK</a>&#160;&#160;&#160;0x00000038U</td></tr>
<tr class="memdesc:ga2af319aa44c2289c2ad189f85adc64af"><td class="mdescLeft">&#160;</td><td class="mdescRight">NVDDR mode.  <a href="group__nandpsu__v1__0.html#ga2af319aa44c2289c2ad189f85adc64af">More...</a><br /></td></tr>
<tr class="separator:ga2af319aa44c2289c2ad189f85adc64af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga735bb9e568cf60cb8900b3b6d8546ebc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga735bb9e568cf60cb8900b3b6d8546ebc">XNANDPSU_DATA_INTF_NVDDR2_MASK</a>&#160;&#160;&#160;0x000001C0U</td></tr>
<tr class="memdesc:ga735bb9e568cf60cb8900b3b6d8546ebc"><td class="mdescLeft">&#160;</td><td class="mdescRight">NVDDR2 mode.  <a href="group__nandpsu__v1__0.html#ga735bb9e568cf60cb8900b3b6d8546ebc">More...</a><br /></td></tr>
<tr class="separator:ga735bb9e568cf60cb8900b3b6d8546ebc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f9ceae9a7e9e68fdf6e99a8bdf6f049"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga2f9ceae9a7e9e68fdf6e99a8bdf6f049">XNANDPSU_DATA_INTF_DATA_INTF_MASK</a>&#160;&#160;&#160;0x00000600U</td></tr>
<tr class="memdesc:ga2f9ceae9a7e9e68fdf6e99a8bdf6f049"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface.  <a href="group__nandpsu__v1__0.html#ga2f9ceae9a7e9e68fdf6e99a8bdf6f049">More...</a><br /></td></tr>
<tr class="separator:ga2f9ceae9a7e9e68fdf6e99a8bdf6f049"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59a9a4d7449ae8c2c8c6dbea6cbc93cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga59a9a4d7449ae8c2c8c6dbea6cbc93cc">XNANDPSU_DATA_INTF_NVDDR_SHIFT</a>&#160;&#160;&#160;3U</td></tr>
<tr class="memdesc:ga59a9a4d7449ae8c2c8c6dbea6cbc93cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">NVDDR mode shift.  <a href="group__nandpsu__v1__0.html#ga59a9a4d7449ae8c2c8c6dbea6cbc93cc">More...</a><br /></td></tr>
<tr class="separator:ga59a9a4d7449ae8c2c8c6dbea6cbc93cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44655d50665d8b4ae9064abcc3dd125b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga44655d50665d8b4ae9064abcc3dd125b">XNANDPSU_DATA_INTF_DATA_INTF_SHIFT</a>&#160;&#160;&#160;9U</td></tr>
<tr class="memdesc:ga44655d50665d8b4ae9064abcc3dd125b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface Shift.  <a href="group__nandpsu__v1__0.html#ga44655d50665d8b4ae9064abcc3dd125b">More...</a><br /></td></tr>
<tr class="separator:ga44655d50665d8b4ae9064abcc3dd125b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DMA Buffer Boundary Register bit definitions and masks</div></td></tr>
<tr class="memitem:ga5a52ede33796646e263eccb79de35e4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga5a52ede33796646e263eccb79de35e4c">XNANDPSU_DMA_BUF_BND_BND_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:ga5a52ede33796646e263eccb79de35e4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA buffer boundary.  <a href="group__nandpsu__v1__0.html#ga5a52ede33796646e263eccb79de35e4c">More...</a><br /></td></tr>
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<tr class="memitem:ga1a30a7722ba522b2ded438107a1b1d85"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_4K</b>&#160;&#160;&#160;0x0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_8K</b>&#160;&#160;&#160;0x1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_16K</b>&#160;&#160;&#160;0x2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_32K</b>&#160;&#160;&#160;0x3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_64K</b>&#160;&#160;&#160;0x4U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_128K</b>&#160;&#160;&#160;0x5U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_256K</b>&#160;&#160;&#160;0x6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XNANDPSU_DMA_BUF_BND_512K</b>&#160;&#160;&#160;0x7U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Slave DMA Configuration Register bit definitions and masks</div></td></tr>
<tr class="memitem:gac7be29ad840652c3fc1e630ccbdf27ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#gac7be29ad840652c3fc1e630ccbdf27ef">XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gac7be29ad840652c3fc1e630ccbdf27ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave DMA Transfer Direction.  <a href="group__nandpsu__v1__0.html#gac7be29ad840652c3fc1e630ccbdf27ef">More...</a><br /></td></tr>
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<tr class="memitem:ga5a94a156a69e8c0f1e4df1b569b4e5fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga5a94a156a69e8c0f1e4df1b569b4e5fd">XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK</a>&#160;&#160;&#160;0x001FFFFEU</td></tr>
<tr class="memdesc:ga5a94a156a69e8c0f1e4df1b569b4e5fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave DMA Transfer Count.  <a href="group__nandpsu__v1__0.html#ga5a94a156a69e8c0f1e4df1b569b4e5fd">More...</a><br /></td></tr>
<tr class="separator:ga5a94a156a69e8c0f1e4df1b569b4e5fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61c0fb19838e962ee547fd98412d4148"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga61c0fb19838e962ee547fd98412d4148">XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK</a>&#160;&#160;&#160;0x00E00000U</td></tr>
<tr class="memdesc:ga61c0fb19838e962ee547fd98412d4148"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave DMA Burst Size.  <a href="group__nandpsu__v1__0.html#ga61c0fb19838e962ee547fd98412d4148">More...</a><br /></td></tr>
<tr class="separator:ga61c0fb19838e962ee547fd98412d4148"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga617818e7f37f8a06b1be1b225745b4aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga617818e7f37f8a06b1be1b225745b4aa">XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK</a>&#160;&#160;&#160;0x0F000000U</td></tr>
<tr class="memdesc:ga617818e7f37f8a06b1be1b225745b4aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA Timeout Counter Value.  <a href="group__nandpsu__v1__0.html#ga617818e7f37f8a06b1be1b225745b4aa">More...</a><br /></td></tr>
<tr class="separator:ga617818e7f37f8a06b1be1b225745b4aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga108ad1c6e87db6855e6ea8a785078e99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nandpsu__v1__0.html#ga108ad1c6e87db6855e6ea8a785078e99">XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK</a>&#160;&#160;&#160;0x10000000U</td></tr>
<tr class="memdesc:ga108ad1c6e87db6855e6ea8a785078e99"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave DMA Enable.  <a href="group__nandpsu__v1__0.html#ga108ad1c6e87db6855e6ea8a785078e99">More...</a><br /></td></tr>
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